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VHDL/SystemC(TM) Cosimulation

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VHDL/SystemC(TM) Cosimulation tool is a member of the Synopsys' SystemC(TM) Design and Verification tool suite named CoCentric® System Studio.
CoCentric® System Studio enables C/C++/SystemC(TM) simulation and VHDL/SystemC(TM) co-simulation at different abstraction level and at various design phases.

The VHDL/SystemC(TM) cosimulation tool allows SystemC(TM) users to use the existing IPs developed in VHDL in their SystemC(TM) designs. It is possible for a SystemC(TM) model to include instantiated modules corresponding to VHDL models.

Using the VHDL/SystemC(TM) cosimulation tool, you can generate interfaces that allow you to cosimulate designs that are a mix of SystemC(TM) modules and VHDL modules.
The cosimulation environment also enables the simulation of a complete system, where the software part is written in C/C++ and the hardware part in object-oriented SystemC(TM).

The cosimulation interface tool provides means by which the SystemC(TM) modelling environment and a HDL simulator can cooperate to simulate a system described in different languages.

It makes possible to use the most appropriate modelling language for each part of the system and verify the correctness of the design. For example, the SystemC(TM) HDL cosimulation interface allows to:

VHDL/SystemC(TM) cosimulation tool is the members of Synopsys' SystemC(TM) Design and Verification tool suite named CoCentric® System Studio.

CoCentric® System Studio