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ODETTE
official home page
ODETTE
home page @ ECSI
Objectives
The high-level objective of the ODETTE project is to support the
competitiveness of the European communication and information
processing industry by reducing the entire design time and cost
of digital embedded HW/SW systems. The prime deliverable of the
ODETTE project is a system for object-oriented HW/SW co-design,
which provides a migration path from object-oriented system specifications
to efficient HW and SW implementations. This method differs from
existing co-design methodologies in its seamless synthesis and
optimisation of the HW design directly from object-oriented specifications,
and its generation of the SW code. Through object-orientated synthesis,
it is possible to develop an early prototype, where the object-orientation
characteristics support reuse of SW and HW components.
ODETTE will aim at avoiding the paradigmatic breaks between system
specification, SW development and HW design. By applying a holistic,
consistent, and automated design methodology to the entire system
on a chip design and functional design verification, an efficient
design exploration and optimisation process will be enabled. In
other words, the same analysis, modelling, and structuring paradigms
will be used for the entire system, regardless of whether the
implementation will be made in software or hardware.
In order to achieve this objective in a sustainable way, the
following sub-goals will be pursued in the project:
- Build and demonstrate a complete working design flow from
system specification to the logic synthesis level, with significant
gains in design time and efficiency, and with minimal overhead
in terms of area.
- Support design and architecture reuse, through a consistent
object-oriented design methodology supported by appropriate
encapsulation and derivation mechanisms of the design modelling
languages.
- Interface to industry standard design flows.
- Implement the design methodology in an efficient tool set,
where not available commercially.
- Provide a tool package for further dissemination and external
exploitation.
- Evaluate and quantify the results of the project.
- Develop and market a complete co-design solution including
HW/SW co-simulation and synthesis tools, using as input object-oriented
description languages for both HW and SW designs.
- Augment the European CAD product offerings with innovative
software in the rapidly increasing market of co-design tools.
These objectives can be achieved by joining forces and competence
on a European level..
Partners:
- European Electronic Chips & Systems design Initiative
(ECSI), France
- Role: Link to large community, standardisation
support.
- IBM Science and Technology Ltd., Israel - International system
and service corporation
- Role: User, methodology specification, evaluator
for modelling and simulation
- OFFIS, Germany - European research Institute
- Role: Project leader, Synthesis implementation,
methodology development
- Siemens ICN S.p.A., Italy - European telecommunication system
house
- Role: User, methodology specification, evaluator
for design and synthesis
- Synopsys LEDA, France - European CAD vendor
- Role: Simulator implementation, tool exploitation
Duration : 3 years . Starting date : June
1st, 2000.
The workplan is structured into four technical workpackages, one
on dissemination and exploitation, and one administrative workpackage.
The consortium has been formed to bring together the necessary expertise
and business interest for this challenge. It consists of a European
telecommunication system house (Siemens ICN S.p.A., Milano, Italy),
an International system house (IBM Science and Technology Ltd. Haifa,
Israel), a European CAD vendor (Synopsys LEDA, Saint Martin d'Heres,
France), a European research institute (OFFIS, Oldenburg, Germany),
and a European CAD standardisation institute (ECSI, Gieres, France).
The project co-ordination is done by OFFIS
Workpackage 1 covers the detailed methodology definition and
preparation of methodological guidelines usable by designers as
well as the creation of reuse libraries coherent with the methodology.
The technical workpackages 2 and 3 are structured according to
the anticipated tool packaging of the project and the intended
specification - implementation - evaluation cycle of the tool
and methodology implementation. The partners will develop tools
to process C++ and Objective VHDL code that complies with the
object-oriented methodology based on class, inheritance, object
instantiation, object communication and polymorphism. The tools
will allow to verify the system description by simulation of functional
tests, and to synthesise it to software and hardware. While Workpackage
2 implements the co-simulation tool, Workpackage 3 deals with
hardware synthesis from object-oriented descriptions in C++ and
Objective VHDL. In fact both workpackages are closely linked by
the common definition and usage of the intermediate format. Workpackage
4 will evaluate the design methodology and the tool set by industrial
applications. The exploitation of the results (Workpackage 5)
will be twofold: Internally by all industrial partners and the
research institute by applying the methodology, libraries and
tools for future product developments as well as by an exploitation
of the test cases, and secondly by external exploitation of the
tool set.
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