Programme

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FORUM PROGRAMME
TECHNICAL PROGRAMME . TUTORIALS . FRINGE MEETINGS

HDL & VUFE

Wednesday, September 1

9h00 - 10h30 Session 1.4: Design Experiences

Chair:
V. Preis, Siemens AG, Germany

9h00-9h30

Invited paper: "HDL's in Industry"
M. Bombana, Italtel SpA, Italy - ABSTRACT

9h30-10h30

Short presentations

S1
Modeling and Simulation of a DTMF receiver/decoder using VHDL-AMS similar language in a Mentor Environment
F.K. Schneider, J. Tortato,
CEFET-PR, Brazil - ABSTRACT

S2
VHDL Core for Synthesis of Phase Accumulators in DDS Applications
René de J. Romero-Troncoso, G. Espinosa-Flores-Verdad
Univ. de Guanajuato, Mexico - ABSTRACT

S3
High Speed Architecture for Image Sequence Processing Described with VHDL
J. Martin, A. Zuloaga, U. Bidarte, J. Ezquerra
Escuela Técnica Superior de Ingenieros, Spain - ABSTRACT

S4
VHDL Test Bench for Digital Image Processing Systems Using a New Image Format
A. Zuloaga, J. Martin, U. Bidarte, J. Ezquerra
Escuela Técnica Superior de Ingenieros, Spain - ABSTRACT

S5
Designing, modeling and implementation of a Controller Area Network (CAN) on a FPGA using VHDL
L. Lemus, J. Garcia, P. Gil
Univ. Politécnica de Valencia, Spain - ABSTRACT

S6
VHDL Design and High-Level Synthesis of an ATM Switch Controller
W. Lange, W. Rosenstiel
Univ. of Tübingen, Germany - ABSTRACT

10h30 - 11h30 Poster Session

11h30 - 12h15 Session 1.5: Mixed Technologies and Mixed Signal

Chair:
A. Vachoux, XEMICS S.A, Switzerland

S1
Mixed Signal IC Development Using MAST, VHDL and VHDL-AMS
O. Zinke
Analogy, Germany - ABSTRACT

S2
Using VHDL-AMS to build a specific analogue behavioral model library
N. Milet-Lewis, J. Charlot, H. Levi, T. Zimmer, A. Laflaquiere, JB Duluc
Univ. de Bordeaux, France - ABSTRACT

S3
An architecture of a Distributed VHDL-AMS Simulator
A. Salem, D. Atef, S. Garcia-Sabiro,
Mentor Graphics, Egypt - ABSTRACT

S4
VHDL-AMS, an unified language to describe Multi-Domain, Mixed-Signal designs. Mechatronic applications
V. Aubert, S. Garcia-Sabiro
Anacad, France - ABSTRACT

12h15 - 13h00 Poster Session

13h00 - 14h00 Lunch

15h00 - 16h00 HDL Late Contributions

16h00 - 17h00 Poster Session

17h00 End HDL & VUFE

9h00 - 10h30	Session 1.4: Design Experiences
Chair:	V. Preis, Siemens AG, Germany
9h00-9h30	Invited paper: "HDL's in Industry" M. Bombana, Italtel SpA, Italy - ABSTRACT
9h30-10h30	Short presentations
S1	Modeling and Simulation of a DTMF receiver/decoder using VHDL-AMS similar language in a Mentor Environment F.K. Schneider, J. Tortato, CEFET-PR, Brazil - ABSTRACT
S2	VHDL Core for Synthesis of Phase Accumulators in DDS Applications René de J. Romero-Troncoso, G. Espinosa-Flores-Verdad Univ. de Guanajuato, Mexico - ABSTRACT
S3	High Speed Architecture for Image Sequence Processing Described with VHDL J. Martin, A. Zuloaga, U. Bidarte, J. Ezquerra Escuela Técnica Superior de Ingenieros, Spain - ABSTRACT
S4	VHDL Test Bench for Digital Image Processing Systems Using a New Image Format A. Zuloaga, J. Martin, U. Bidarte, J. Ezquerra Escuela Técnica Superior de Ingenieros, Spain - ABSTRACT
S5	Designing, modeling and implementation of a Controller Area Network (CAN) on a FPGA using VHDL L. Lemus, J. Garcia, P. Gil Univ. Politécnica de Valencia, Spain - ABSTRACT
S6	VHDL Design and High-Level Synthesis of an ATM Switch Controller W. Lange, W. Rosenstiel Univ. of Tübingen, Germany - ABSTRACT

11h30 - 12h15	Session 1.5: Mixed Technologies and Mixed Signal
Chair:	A. Vachoux, XEMICS S.A, Switzerland
S1	Mixed Signal IC Development Using MAST, VHDL and VHDL-AMS O. Zinke Analogy, Germany - ABSTRACT
S2	Using VHDL-AMS to build a specific analogue behavioral model library N. Milet-Lewis, J. Charlot, H. Levi, T. Zimmer, A. Laflaquiere, JB Duluc Univ. de Bordeaux, France - ABSTRACT
S3	An architecture of a Distributed VHDL-AMS Simulator A. Salem, D. Atef, S. Garcia-Sabiro, Mentor Graphics, Egypt - ABSTRACT
S4	VHDL-AMS, an unified language to describe Multi-Domain, Mixed-Signal designs. Mechatronic applications V. Aubert, S. Garcia-Sabiro Anacad, France - ABSTRACT