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FORUM PROGRAMME
TECHNICAL PROGRAMME . TUTORIALS . FRINGE
MEETINGS . HANDS-ON LABS
TUTORIALS
Monday, August 30, 13h-18h30
Presenter: Oz Levia, Vice President, Engineering, Improv Systems, Inc., USA.
SOC is a reality. For many design teams this reality is a mixed blessing. While silicon capacity allows and demand integration of an ever larger portion of the over all system onto a single die, the task of designing, verifying, and maintaining such a design is increasingly taxing and complex.
In this tutorial we present a new approach to embedded system design for consumer electronics: the Programmable System Architecture (PSAT). Using the PSA, system application design will be done using Virtual IPT objects and a framework for composing a complete application from a collection and hierarchy of Virtual IP objects. Once the system application is specified it can be verified and mapped, using an advanced compiler, onto a system chip platform. The PSA is a pre-made architecture that can be configured and programmed post manufacturing. This approach allows system design to focus on the system specifications without concern for HW / SW co-design and partitioning. System applications are written in Java and can be verified a Java native environment. Once the application is mapped to the PSA, the result is an application specific IC. The PSA approach has the advantages of very rapid time to market, high performance and low design cost and risk.
The focus of this tutorial is to illustrate how a system application designers will use the PSA application development framework to develop embedded consumer IC.
Oz Levia is a co-founder and vice president of engineering of Improv Systems, Inc. He holds a BS and MS in computer science from the University of Minnesota and Boston College respectively. Oz has been active in the EDA tools market for over 10 years must recently focusing on issues concerning intellectual property use in system design. Over the years Oz presented many successful papers and tutorials on a wide range of subjects such as VHDL simulation, synthesis, gate level timing (VITAL) and IP use in system design in many conferences and workshops world wide.
Presenters: Ralf Seepold, Natividad Martínez Madrid, FZI Karlsruhe, Germany - Kevin O'Brien, LEDA S.A., France
The design of microelectronic systems is heavily driven by the fact that transistor and feature size have been constantly decreased over the years, while frequency and density have been increased. This gain has been supported by the development of new technologies and manufacturing equipment, which provide mechanisms to improve design efficiency. As a consequence of this progress, development environments have been evolved, which are very complex. Since the major key to the success is to shorten time, the prosperity of a product is also closely related to the necessity of efficient methodologies to create new or enhanced products to an aggressive time-scale.
Intellectual Property (IP) and design reuse methodologies are expected as key enablers to face both short and long term development objectives. Due to the fact that the level of complexity constantly increases reuse of approved designs and the design of efficiently reusable components become the most crucial enterprise.
This tutorial will present a survey of IP and reuse and it will also include a brief presentation and demonstration of Proton, a programmable design rule checker. Proton's rule checker is intended to be used at the top end of the design flow to ensure that VHDL and/or Verilog models are compatible with the methodology and design flow in place, and this is done before beginning time-consuming simulation-synthesis iterations.
Ralf Seepold received his M.S. degree in Computer Science from the University of Paderborn in 1992 and his Ph.D. degree from the University of Tübingen in 1997. In 1992 he joined the computer science and research center FZI in Karlsruhe. In 1997, he became project leader, and since 1999, he is head of the department "Microelectronics System Design". In 1998, he became director of the German ECSI Office at FZI that is a representative of VSI Alliance. He served as a founder and general chair of the "Workshop Reuse Techniques for VLSI Design" in 1997 and 1998. Since 1998, he is member of the steering group for the "MEDEA/Esprit Conference". In 1998, he also served as a topic co-chair for DATE on design reuse, and in 1999, he was topic chair for "Design reuse and IP" at DATE.
Kevin O'Brien graduated with a Masters Degree in electronics from the University of Limerick, Ireland, in 1989. He completed his Ph.D in system-level synthesis at the TIMA laboratory, Grenoble, France in 1993. Since then, he has been working at LEDA S.A. in Grenoble where he is currently product manager of LEDA's end-user product line. His main interests include design methodologies, system-level synthesis and hardware description languages.
Presenters: Mary Sheeran, Prover Technology, Sweden - Nicolas Halbwachs, Verimag, France
We present the synchronous data-flow programming language LUSTRE and its use in the design and analysis of control programs and hardware. LUSTRE is a simple and elegant programming language, designed specifically for programming reactive systems. It also works well as a hard-ware description language. It is gaining ground in real industrial applications; for example, at Aerospatiale, LUSTRE is used to write Airbus software. Our thesis is that LUSTRE deserves to be more widely known in the system design community.
Here, we present the programming language LUSTRE from a practitioner's viewpoint. Participants learn both how to describe systems and how to specify the required properties of systems in the programming language. Using the idea of a synchronous observer, we avoid the need for a separate logic in which to express program properties. Participants first write and run small LUSTRE programs. Next, they learn how to formally (and automatically) verify their programs using synchronous observers and the LESAR and LUCIFER tools. LESAR is based on standard model checking methods, while LUCIFER combines model checking with inductive proof. We explain the main ideas underlying these verification techniques, and also provide hands-on exercises in programming and verification.
Mary Sheeran is a senior researcher at Prover Technology AB, Sweden. She is also a Professor in computing science at Chalmers University of Technology, Gothenburg.
She studied electronic engineering at Trinity College Dublin, and formal methods at Oxford University. For her doctorate, she combined these two topics, to develop a synchronous programming language for describing and reasoning about hardware. She received her doctorate in 1984, and joined Prover Technology in 1997.
Her research continues to be about hardware description languages, and how best to design them to ease formal verification.
Nicolas Halbwachs is "Research Director" at CNRS, working at Verimag Laboratory in Grenoble.
His first work was on abstract interpretation of programs, with Patrick Cousot. In 1984, he obtained his "State Thesis", at "Institut National Polytechnique de Grenoble", under the supervision of Paul Caspi, on a formal model of real-time system behavior.
Since then, he was one of the main designers of the synchronous data-flow language Lustre. He successively worked on the language design, compilation to software and hardware, and on verification techniques for synchronous programs. He is strongly involved in the industrial transfer of Lustre technology.
Presenter: Ahmed Amine Jerraya, TIMA Laboratory, France Hardware/Software Co-design has become a strategic technology for modern electronic systems, from VLSI single chips containing embedded cores via boards to large distributed systems made of a heterogeneous network of processors communicating via sophisticated protocols. Co-design is the enabling technology for industry and may also be the bottleneck for faster progress. This tutorial is designed to provide the attendees with a comprehensive background on the state of the arts and the future of co-design.
This tutorial is structured into two parts :
Dr. Ahmed Amine Jerraya received the Ph.D. degree from the University of Grenoble in 1983.
In 1998, he co-founded AREXSYS, a start-up co-design company and he is the Vice-General Chair of DATE 2000. He received the Best Paper Award at the 1994 ED&TC for his work on Hardware/Software Co-simulation. He also led the R&D of the successful behavioral synthesis tool AMICAL and the COSMOS co-design environment.
Dr. Jerraya is currently managing the System-Level Synthesis group of TIMA Laboratory and has the grade of Research Director within the CNRS.
Presenter: Michael D. Ciletti, University of Colorado at Colorado Springs, USA
Designers facing the challenges of the next millennium must exploit the rapidly advancing technology of deep sub-micron ASICs. In this scenario, it is forseeable that that hardware description languages will continue to shape design methodologies at all levels of integration, from PLDs to ASICS and full-custom parts. The impact of HDLs will expand as more designers embrace HDL-based tools for digital design, and as HDLs supporting mixed design become stable. Many of today's design flows for ASICs and FPGAs typically rely on synthesis tools that optimize and map Verilog HDL descriptions of digital circuits into physical netlists, thereby meeting specifications, reducing the design cycle, integrating third-party IP, and increasing the opportunity for design exploration. The growing acceptance of this design paradigm suggests that an increasing number of designers will need to be productive users of Verilog in the forseeable future.
This half-day tutorial will give designers attending FDL'99 an intensive overview of the Verilog language. HDLs are not the same as procedural programming languages, and designers do not need to have prior experience with a programming language before using an HDL.
The objectives of this tutorial are twofold:
Several examples of combinational and sequential circuits will illustrate
structural and behavioral modeling with the language, and serve as platforms
for presenting topics and results in synthesis with Verilog. The presentation
will cover hardware-related semantics and syntax, and the conceptual framework
of event-driven simulation and concurrency in language-based descriptions
of digital circuits. A segment of the presentation will identify relationships
between Verilog and VHDL constructs to facilitate a bi-lingual HDL dialogue
among attendees. Pending the availability of suitable hardware and software
tools at FDL'99, the tutorial will include self-paced exercises that attendees
can use offline to explore concepts presented in the talk.
Dr. Ciletti is a professor of electrical and computer engineering at the University of Colorado at Colorado Springs, where he teaches course in synthesis, synthesis algorithms, and VLSI circuit design methodology using a variety of tools and languages, including the Verilog HDL and VHDL. Dr. Ciletti has consulted and taught HDLs to designers at companies and universities in the U.S., Asia, and Europe. He is the author of the textbook: Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, 724 pp., published by Prentice-Hall Pub. Co., February 1999.
Prof. Michael D. Ciletti, Dept. of Electrical and Computer Engineering, University of Colorado at Colorado Springs , P.O. Box 7150, Colorado Springs, Colorado 80933-7150, USA. Email: ciletti@vlsic.uccs.edu