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FORUM PROGRAMME
TECHNICAL PROGRAMME . TUTORIALS . FRINGE
MEETINGS
HDL & VUFE
Tuesday, August 31
| 9h00 - 10h45 | Opening Session |
Chair: |
J. Mermet, ECSI/TIMA, France |
| Welcome and General Information A. Mignotte, ENS-Lyon, France, Co-organization Chair, D. Sciuto, Politecnico di Milano, Italy, HDL & VUFE Chair, R. Seepold, FZI, Germany, VCDR Chair, and E.Villar, Universidad de Cantabria, Spain, SSDL Chair | |
9h30 |
Keynote Speakers The MEDEA EDA Roadmap Keynote Speaker 2 |
| 10h45 - 11h00 | Break |
| 11h00 - 12h00 | Session 1.1: Synthesis Methodology |
Chair: |
B. Conq, CNET-France Telecom, France |
S1 |
A VHDL Component Model for Mixed Abstraction Level Simulation and Behavioral
Synthesis C. Hansen, W. Rosenstiel, O. Bringmann FZI, Germany - ABSTRACT |
S2 |
Synthesizing Hardware from Object-Oriented Descriptions M. Radetzki, W. Nebel OFFIS Oldenburg, Germany - ABSTRACT |
S3 |
VHDL Dynamic Loop Synthesis M.F. Albenge, D. Houzet, ENSEEIHT, France - ABSTRACT |
S4 |
Pre-synthesis circuit activity analysis for VHDL D. Markland, T. Kazmierski, Univ. of Southampton, UK - ABSTRACT |
S5 |
Automatic Interface Generation among VHDL Processes in Hardware/Software
Co-Design E. Barros, C. Araujo UFPE, Brazil - ABSTRACT |
| 12h00 - 13h00 | Poster Session |
| 13h00 - 14h00 | Lunch |
| 14h00 - 15h00 | Session 1.2: Simulation and Estimation Tools |
Chair: |
A. Pawlak, Silesian Technical University, Poland |
S1 |
VHDLP: constraint specification and performance evaluation for design-tuning P. Bakowski, G. Ramstein, Y. Nadreau IRESTE, France - ABSTRACT |
S2 |
An Adaptable VHDL-AMS Compiler Front-end A. Windisch, W. Ecker, J. Mades, T. Schneider, K. Yang Siemens, Germany - ABSTRACT |
S3 |
A Makefile Generator for VHDL Models under Consideration of Hierarchical
Names, Identifier-Visibility and Identifier-Hiding W. Ecker, J. Mades, T. Schneider, A. Windisch, K. Yang, Siemens, Germany - ABSTRACT |
S4 |
Techniques for Improving the HDL Simulation Performance A. Morawiec, J. Mermet TIMA Laboratory, France - ABSTRACT |
S5 |
Using and teaching VHDL on Internet P. Bakowski IRESTE, France - ABSTRACT |
| 15h00 - 16h00 | Poster Session |
| 16h00 - 17h00 | Session 1.3 : Formal Verification |
Chair: |
D. Sciuto, Politecnico di Milano, Italy |
S1 |
Formal verification of VHDL using VHDL-like ACL2 models D. Borrione, P. Georgelin TIMA Laboratory, France - ABSTRACT |
S2 |
Specification of Embedded Monitors for Property Checking A. Allara, M. Bombana, S. Comai, B. Josko, R. Schör, D. Sciuto Italtel S.p.A., Italy - ABSTRACT |
S3 |
HXML - A new Approach to Managing Hardware
Information A. Zamfirescu, J. Karrfalt Alternative System Concepts, USA - ABSTRACT |
| 17h00 - 17h15 | Break |
| 17h15 - 18h30 | Panel : HDL Standards Roadmap for the Twenty-First Century |
Chair: |
V. Berman, IEEE DASC, USA |
| S. Bailey, VASG Chair, D. Brophy, DPC Chair, A. Vachoux, VHDL AMS, D. Barton/S. Schulz, SLDL, G. Gorla, ECSI |
| 18h00 | End |