Programme

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FORUM PROGRAMME
TECHNICAL PROGRAMME . TUTORIALS . FRINGE MEETINGS

VCDR

Thursday, September 2

9h00 - 10h30 Session 2.3: Standardization of VCs

Chair:
R. Seepold, FZI, Germany

S1
An Overview of the Open Model Interface
G. Moretti, Veribest Inc., USA - ABSTRACT

S2
Challenges and Solutions of VC-based System Architecture
M. Genoe, Alcatel Microelectronics, Belgium - ABSTRACT

S3
VC Interfaces
K. Hashmi, ICL, UK - ABSTRACT

10h30 - 11h30 Poster Session

11h30 - 13h00 Panel: IP Re-use for SoC: how is it progressing?

Chair:
L. Drenan, Cadence, USA

Panelists:
Fadi Azhari, Sun Microelectronics
Mark Genoe, Alcatel
Oz Levia, Improv Systems
Yves Mathys, Motorola
Gabrielle Saucier, Design and Reuse
Andy Travers, VCX
Bob Terwilliger, ARC Cores

13h00 - 14h00 Lunch

14h00 - 15h00 Session 2.4: IP Measurements and Quality

Chair:
S. Olcoz, Sidsa, Spain

S1
A VHDL Analysis Environment for Design Reuse
C. Costi, M. Miller
Univ. of Victoria, Canada - ABSTRACT

S2
ARDID: A Tool for the Quality Analysis of VHDL based Designs
Y. Torroja, C. Lopez, M. Garcia, T. Riesgo, E. de la Torre, J. Uceda
Univ. Politecnica de Madrid, Spain - ABSTRACT

S3
Evaluation of VHDL-Based Design Reuse Through-Block Analysis
S. Bernardi, W. Fornaciari, S. Minonne, F. Salice, M. Vincenzi
Politecnico di Milano, Italy - ABSTRACT

15h00 - 15h15 Break

15h15 - 16h15 Session 2.5: IP Modeling and Libraries

Chair:
W. Nebel, OFFIS-Oldenburg, Germany

S1
Cryptographic Reuse Library
A. Schubert, W. Anheir
Univ. of Bremen, Germany - ABSTRACT

S2
Automated Generation of Flexible and Reusable Virtual Component Models in VHDL
A. Pulka
Silesian Technical Univ., Poland - ABSTRACT

S3
An Approach to Specification and Synthesis of adaptive Interfaces of Reusable Hardware Modules
R. Siegmund, D. Mueller
Technical Univ. of Chemnitz, Germany - ABSTRACT

16h15 - 17h15 Poster Session

17h15 - 18h30 Session 2.6: Invited Papers

Chair:
S. Maginot, LEDA S.A., France

Invited 1
Software IP in Embedded Systems
F. Rammig
Univ. of Paderborn, Germany - ABSTRACT

Invited 2
Capturing the Potential of System on a Chip
B. Terwilliger
ARC Cores Inc., UK - ABSTRACT

18h30 End

9h00 - 10h30	Session 2.3: Standardization of VCs
Chair:	R. Seepold, FZI, Germany
S1	An Overview of the Open Model Interface G. Moretti, Veribest Inc., USA - ABSTRACT
S2	Challenges and Solutions of VC-based System Architecture M. Genoe, Alcatel Microelectronics, Belgium - ABSTRACT
S3	VC Interfaces K. Hashmi, ICL, UK - ABSTRACT

11h30 - 13h00	Panel: IP Re-use for SoC: how is it progressing?
Chair:	L. Drenan, Cadence, USA
	Panelists: Fadi Azhari, Sun Microelectronics Mark Genoe, Alcatel Oz Levia, Improv Systems Yves Mathys, Motorola Gabrielle Saucier, Design and Reuse Andy Travers, VCX Bob Terwilliger, ARC Cores

14h00 - 15h00	Session 2.4: IP Measurements and Quality
Chair:	S. Olcoz, Sidsa, Spain
S1	A VHDL Analysis Environment for Design Reuse C. Costi, M. Miller Univ. of Victoria, Canada - ABSTRACT
S2	ARDID: A Tool for the Quality Analysis of VHDL based Designs Y. Torroja, C. Lopez, M. Garcia, T. Riesgo, E. de la Torre, J. Uceda Univ. Politecnica de Madrid, Spain - ABSTRACT
S3	Evaluation of VHDL-Based Design Reuse Through-Block Analysis S. Bernardi, W. Fornaciari, S. Minonne, F. Salice, M. Vincenzi Politecnico di Milano, Italy - ABSTRACT

15h15 - 16h15	Session 2.5: IP Modeling and Libraries
Chair:	W. Nebel, OFFIS-Oldenburg, Germany
S1	Cryptographic Reuse Library A. Schubert, W. Anheir Univ. of Bremen, Germany - ABSTRACT
S2	Automated Generation of Flexible and Reusable Virtual Component Models in VHDL A. Pulka Silesian Technical Univ., Poland - ABSTRACT
S3	An Approach to Specification and Synthesis of adaptive Interfaces of Reusable Hardware Modules R. Siegmund, D. Mueller Technical Univ. of Chemnitz, Germany - ABSTRACT

17h15 - 18h30	Session 2.6: Invited Papers
Chair:	S. Maginot, LEDA S.A., France
Invited 1	Software IP in Embedded Systems F. Rammig Univ. of Paderborn, Germany - ABSTRACT
Invited 2	Capturing the Potential of System on a Chip B. Terwilliger ARC Cores Inc., UK - ABSTRACT