CONFERENCE REPORT
by Prof. Anne Mignotte
FDL'99 is the second edition of the Forum on Design Languages. It groups three events around languages for microelectronic design: HDL & VUFE (Hardware Description Languages & VHDL User Forum in Europe), VCDR (Virtual Component and Design Reuse) and SSDL (System Specification & Design Languages).
From August 30th to September 3rd, 190 people attended FDL'99 at Ecole Normale Supérieure de Lyon (ENS Lyon), in the gastronomic city of Lyon France. Most of them came from Europe (mainly France and Germany); beside, we also welcome people from Israel, Egypt, India, Canada, Japan, USA, Turkey or Mexico. We enjoyed the mixture between academic and industry attendees. The long poster sessions with coffee breaks were the opportunity for them to share experiences.
FDL'99 started with half-day tutorial linked to the three events of the forum. Four tutorials covered the advanced topics in design languages -Verilog, Lustre, Java- and Intellectual Property (IP) reuse.
The opening keynote speaker was Joseph Borel from ST Microelectronics. He described the MEDEA EDA Roadmap. Two other keynote speakers added more insight on topics linked respectively to VCDR and SSDL. Jürgen Haase from SICAN developed the use of virtual component from research to business and Jean-Raymond Abrial from STERIA introduced the B-method, which is a formal approach for system design. Interesting panels gave the opportunity to have intensive discussions on hot topics: "IP reuse for System on Chip (SoC)" for VCDR, "HDL Standards Roadmap for the 21st century" for HDL & VUFE and "Languages and Semantics for System Level Design Languages" for SSDL.
Hardware Description Languages & VHDL User Forum in Europe (HDL&VUFE)
The first event HDL&VUFE took place on August 31st and September 1st. It offered a snapshot of the status of practical use of VHDL and other hardware description languages. This year, it mainly focused on high levels of abstraction, mixed signal designs and tools allowing effective hardware description. Two main areas were concerned: modelling -namely formal specification or simulation- and languages for automated design -namely synthesis and testing-.
Virtual Component and Design Reuse (VCDR)
The second part of FDL'99 hosted VCDR on September 1st and 2nd. It addressed all relevant levels of abstraction, mixing digital and analog virtual components reuse, defining methodologies and tools for reuse of IP, as well as library management and rapid prototyping. The emerging standards were also presented.
System Specification & Design Languages (SSDL)
Finally, SSDL lasted from September 2nd to 3rd. It developed an industry-wide consensus for key problems like System on Chip (SoC). Therefore, it addressed the industry standards for the description of heterogeneous systems (digital and analog hardware, hardware software Co-Design and optical devices). All these presentations and discussions were completed by practical hands-on-labs from the major CAD tool vendors: Analogy, Cadence, Diagonal Systems, ETSI Industrials, Frontier Design, Leda, Mentor graphics and Synopsys.
The attendees voted to select the best paper of the forum. It was "An Approach to Specification and Synthesis of adaptive Interfaces of Reusable Hardware Modules" written by R. Siegmund and D. Mueller from the Technical University of Chemnitz in Germany. The best poster award was attributed to the poster entitled: "Techniques for Improvement of the HDL Simulation Performance" by A. Morawiec and J. Mermet; the second and third places were attributed to the winning paper presentation and "ARDID: a Tool for the Quality Analysis of VHDL Based Designs" written by Y. Torroja, C. Lopez, M. Garcia, T. Riesgo, E. De la Torre and J. Uceba from the Universidad Politecnica de Madrid, in Spain.
I would like to warmly thank all the member of the organising committee who efficiently helped me to make this event a success. I also want to pay homage to Ralf Seepold for his active participation as the chair of FDL'99 and to his assistants on the different events namely Donatella Sciuto for HDL&VUFE and Eugenio Villar for SSDL.
I would like also to express particular thanks to all the sponsors - ECSI, ENS-Lyon, Cadence, Mentor Graphics, Synopsys, and all the co-sponsors who helped to make the event successful and also actively contributed to its publicity.
Next year, FDL2000 will take place in Tübingen, in Germany from September 4th to 8th, 2000. I invite you to have a look at our Web site for more information: www.ecsi.org/ecsi/fdl
FDL Success in Detail
Registration at the Conference
Full conference: 95
Students: 23
Two days: 3
One day: 27
Tutorial only: 2Total: 190
Tutorials Total: 39
Number of countries represented:: 22 - Australia, Austria, Belgium, Brazil, Canada, Egypt, Finland, France, Germany, India, Israel, Italy, Japan, Mexico, Poland, Slovakia, Spain, Sweden, Switzerland, Turkey, UK, USA
Hands-on Labs: Analogy, Cadence, Diagonal Systems, ETSI Industriales,
Frontier Design, LEDA S.A., Mentor Graphics, Synopsys