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FORUM PROGRAMME
TECHNICAL PROGRAMME . TUTORIALS . FRINGE
MEETINGS . HANDS-ON LABS
HANDS-ON LABS
| Time | Room | Tuesday 31/8 | Wednesday 1/9 | Thursday 2/9 | Friday 3/9 |
A.M. |
106 | LEDA | Synopsys | Diagonal Systems | ETSI |
| 109 | Cadence | Frontier Design | |||
P.M. |
106 | Mentor Graphics | Analogy | ||
| 109 |
Computers available: 10 SparcStation 5 running Solaris 2.6 in room 106, and 15 PC Dell GX1 running NT 4.0 SP3 in room 109.
ANALOGY: "VHDL-AMS Modeling and Simulation"
Instructor: Olaf Zinke <ozinke@analogy.com>
Summary:
In March 1999 the Analog and Mixed Signal extension of VHDL was released by the IEEE committee as the 1076.1 standard. During this Lab the participants will learn the most important syntactic elements of this new standard language for the description of analog and mixed-signal behavior. After a brief introduction of the modeling and structural concepts of VHDL, the students will get a more detailed view of the syntax elements that are most important in the analog and mixed-signal domains. This theory talk is followed by a practical part. Here the students will create their own VHDL-AMS design. They will use the new VHDL-AMS simulator VeriasHDL of Analogy to test their design examples.
CADENCE: "Virtual Component Co-Design: VCC"
Instructor: Laurence Meunier <meunier@cadence.com>
Summary:
Answering the system level design crisis The CIERTO Virtual Component Co-Design (VCC) offers the technology that is essential to manage the system level integration and verification crisis in the delivery of electronics systems. Key benefits are:
VCC is the industry's first system level development environment for HW/SW Co-Design and IP reuse. VCC allows designers to confirm critical architectural decisions, such as the hardware and software partitioning of system functionality, early in the design of their first generation and derivative products.
Used as a technology for configuration of SOC Integration Platforms, VCC allows system companies and silicon vendors to optimize product specifications, shorten development cycles, and capitalize on the increased capabilities offered by multi-million gate integrated circuits. VCC also provides software and hardware component vendors with a "delivery vehicle" for promoting and distributing critical information to ensure successful "design-in" by their customers.
A Complete Design Flow from System to Implementation
VCC is part of a complete design flow and provides close integration with leading IP creation tools such a C++, SDL and Cadence's CIERTO Signal Processing Worksystem (SPW). VCC's powerful links to Implementation bridge the gap between system-level design, implementation and verification using HW/SW co-verification and HDL simulators.
DIAGONAL SYSTEMS: "VHDL testbench design workshop using BestBench"
Instructor: Loys Gindraux
Summary:
This workshop will introduce the attendee to the use of BestBench, a tool which facilitates and automates the creation of behavioral self-checking and reactive VHDL testbenches to speed-up and automate the verification of the RTL circuit.
BestBench allows designers to easily define test cases in terms of stimuli data streams and optionally expected circuit responses. This description is automatically converted in a simulation-ready, reactive and algorithmic self-checking testbench. One of the big advantages is that with BestBench you can mix VHDL and graphical waveform procedures to ease the testbench creation.
Once the specification is done, you can simulate and debug the testbench even without the RTL circuit. This enables the testbench debug separately from the circuit debug. So, when you combine circuit and testbench, you already know that the test bench will work as required. Once the testbench is debugged, it is used to debug the circuit. Mismatches between circuit behavior and expected responses are highligted which focuses the circuit debug process. Generation of regression tests and general discussion on testbench design methodologies are part of the workshop.
Prerequisite : working knowledge of VHDL (at least RTL/synthesysable subset).
ETSI Industrials: Using ARDID to Asses the Quality of a VHDL Design
Instructor: Yago Torroja <yago@upmdie.upm.es>
Summary:
In this hands-on-lab, ARDID, a tool developed to help in the VHDL design flow of complex systems on silicon will be presented. This tool is aimed to help designers and Project Managers to improve the quality of their VHDL based designs.
The tool includes several checkers to analyse the quality of the VHDL descriptions from several points of view. Some of the checkers are oriented toward design reliability, analysing aspects like clock and reset schema, use of latches and flip-flops, connectivity, use of tri-state signals, etc. Other checkers are intended to analyse the design style, consistency of sensitivity list, use of hard-coded values, etc. Finally, a part of the tool is intended to measure the quality of the test-benches used in the functional validation of the design.
During the lab, the main features of the tool will be presented, using the tool to analyse different real VHDL examples. The examples used will show how the tool could help to discover design errors and improve overall design quality.
FRONTIER Design: "Using A|RT to design hardware starting from C"
Instructor: Ivo Van Gelder <ivo_vangelder@frontierd.com>
Summary:
Frontier Design's unique Algorithm to Silicon methodology is embodied in its A|RT product family. A|RT stands for Algorithm to RT and provides a significant productivity increase for the design of leading edge telecom, consumer and multimedia products.
The Hands-on-lab will make you familiar with Frontier Design's A|RT methodology and tools. In a step-by-step fashion you will learn how to translate a C description into an RTL HDL description using A|RT Builder, how to refine the C description with fixed-point data types from A|RT Library, and how to optimize the resulting hardware by applying resource sharing. You will also be introduced to the Architectural Synthesis Toolkit that provides an automated path from behavioral C models to RT-level descriptions.
Prerequisites for the lab are a basic knowledge of the C language, as well as a basic understanding of either VHDL or Verilog.
LEDA: "PROTON: A Programmable HDL Design Rule Checker"
Instructor: Rabih Saade <rabih@leda.fr>
Summary:
This lab will give an overview of PROTON, the programmable design rule checker for VHDL and Verilog. Participants will first learn of the need for such a tool in today's design flows. They will then be led through an example that shows both the checking and the programming aspects of PROTON. Then, the language used to program design rules will be explained and participants will be asked to program and check a set of basic design rules.
MENTOR Graphics
Instructor: Pascal Widomski <pascal_widomski@mentorg.com>
Summary:
SYNOPSYS: "Eagle"
Instructor: David Dick <ddick@synopsys.com>
Summary:
The Eagle hardware/software co-verification tools from Synopsys allow system designers to begin the integration of the hardware and software at a much earlier stage in the design process. With Eagle, it is possible to start testing system assumptions starting immediately after partitioning, continuing through prototyping. Eagle offers unsurpassed modeling support for embedded microprocessor architectures including ARM, as well as an open interface to support Industry standard HW/SW environments.
The HW/SW co-verification workshop will give an overview of the Eagle environment and introduce a virtual single computer based on a ARM7 embedded core instruction set simulator, connected to VCS for hardware simulation and a software debugger (Armulator). The hands-on labs will show the main features of the HW/SW debugging environment working interactively, with the HDL simulator and the native debugging environment from ARM.
Work Shop Schedule:
9:15 : Coffee and introduction
9:30 : An introduction to HW/SW Co-Verification
10:15 : Co-Verification processor model trade-offs
10:30 : Coffee break
10:45 : Eagle/ARM Integration
11:00 : Hands on work shop
12:00 : Q&A session