{ Useful Links}

Call for Contribution (PDF format)
Advance Programme (PDF format)

Several events are taking place in Stuttgart at the same time as FDL'08
Book your hotel early ! Special FDL rates available, see the Venue page.

Online registration is open till September 17th, 2008.


{ Important Dates}

FDL is the premier international forum to present research results, to exchange experiences, and to learn about new trends in the application of specification, design and verification languages as well as of associated design and modelling methods and tools for integrated circuits, complex HW/SW embedded systems, and heterogeneous systems. Modelling and specification concepts push the development of new methodologies for design and verification to system level; thus providing the means for model-driven design of complex information processing systems in a variety of application domains. The aim of FDL is to cover several related thematic areas and to give an opportunity to gain up-to-date knowledge in this fast evolving, essential area in system design and verification.

FDL is celebrating its tenth birthday in the year of 2008. It continues a series of successful events that have taken place in Lausanne, Lyon, Tübingen, Marseille, Frankfurt am Main, Lille, Darmstadt, and Barcelona. This year, FDL is organized in technical cooperation with the the IEEE and IEEE Computer Society Technical Committee on Design Automation (TCDA), IEEE France Section, and IEEE Germany Section. FDL papers will be available online via IEEEXplore after the conference.

FDL’08 will be held from September 23 to 25, 2008, at the ‘Universität Stuttgart’. Stuttgart, the state capital of Baden- Württemberg, is a booming community in the Southwest of Germany. The Stuttgart region is the home of world famous companies
in the Automotive, Telecommunications, and Information Technology sectors as well as many internationally operating small and medium sized companies. The ‘Universität Stuttgart’ is a research university with a long tradition and a consistently strong position in the fields of Computer Science and Electrical Engineering. Beyond that, Stuttgart offers the visitor numerous vineyards and forests stretching all the way to the city center, famous mineral water springs and fountains, and cultural offerings including its renowned State Opera, Ballet and the exquisite art collections at the State Gallery and Gallery of Stuttgart; see www.stuttgarttourist.de .

Martin Radetzki
General Chair


{ The Thematic Areas}

PDV TA: Property-Driven Design, Verification & Debug
Chair: Dominique Borrione – TIMA Laboratory, France, Dominique.Borrione@imag.fr

The assertion of formal properties provides a uniform expression of expected system behaviour, or constraints that are assumed on the environment, for a variety of design tasks: verification of functional correctness, generation of test stimuli, synthesis of observation monitors and on-line tests, model checking on the reachable state space, direct synthesis from assertions, etc. Standardized formalisms such as PSL and SystemVerilog, defined with trace operational semantics, were initially intended for synthesizable RTL; their application is now considered at transaction levels and for mixed system designs. The PDV technical area welcomes research contributions, tool demonstrations, reports on standardization activities and effective applications in all aspects of innovative property expression and processing, with an emphasis on frontier design levels, verification, automatic synthesis and mechanized debug aids.


CSD TA: C/C++-Based System Design
Chair: Frank Oppenheimer – OFFIS e.V., Germany, Frank.Oppenheimer@offis.de

The CSD TA addresses language-based modelling and design techniques for simulation, debugging, transformation, and analysis of hardware/software embedded systems. C/C++ based design methodologies are entering productive industrial design flows especially after the IEEE standardization of SystemC. Hence, the lion share of contributions use SystemC and its extensions to illustrate the scientific approach. However, articles using languages like UML, functional languages, System Verilog are very welcome, especially if they address interoperability between modelling languages and heterogeneous models of computations. Topics of interest also include embedded software modelling techniques and technology or domain specific approaches, e.g. for signal processing applications or reconfigurable computing platforms. New mechanisms for abstraction like transaction level modelling (TLM) or SPIRIT and their implications on IP-based system design or system synthesis are in the scope of this workshop as well as innovative industrial case studies.


DCS TA: Design of Discrete and Continuous Embedded Systems
Chair: Sorin A. Huss – Technische Universität Darmstadt, Germany, huss@iss.tu-darmstadt.de

Modern information processing systems frequently combine analog, RF, power electronic, or even non-electrical components with complex digital hardware and an increasing share of software into an embedded system. The aggregation and tight interaction of such components within one data processing system is a challenge: specification, modelling, simulation, (symbolic) analysis, verification, design, (virtual) prototyping, or even synthesis of analog, mixed-signal, and heterogeneous systems, i.e., embedded systems processing both discrete and continuous signals, are highly complex issues. Furthermore, physical effects are of an increasing impact and have to be considered even at system level. Languages, models, representations, and tools such as VHDL-AMS, Verilog-AMS, SystemC-AMS, Modelica, Matlab/Simulink, or Hybrid Automata are emerging to support such issues starting from transistor level analog circuit up to system level design. The DCS Thematic Area aims at presenting latest research activities, design experiences, and standardization issues related to these topics.


UMES TA: UML and MDE for Embedded System Specification & Design
Chair: Pierre Boulet – LIFL, Lille, France, Pierre.Boulet@lifl.fr

Model driven methods, mostly based on the Unified Modelling Language, increasingly support semi-formal methods for system level design of complex embedded systems including highly programmable platforms and heterogeneous Systems-on-Chip. Current design methods do not close the gap from specification to (automatic) synthesis yet. UMES related research topics in this field are Executable UML, model driven development, model transformations, UML semantics, meta-modelling (e.g., for SystemC and other System Description Languages or HDLs), UML profiles (SysML, MARTE, UML for SoC, ...), formalization of UML towards domain specific languages for simulation and synthesis. Other welcomed topics are standardization work, modelling languages for real-time and embedded systems, model driven techniques for performance analysis, validation and verification, SDL, AADL, OCL, XMI and practical design experiences with UML or model driven engineering (MDE) approaches.