{ Useful Links}
Call for Contribution (PDF format)
No more papers are accepted - Go
to the submission page to check you
paper status
The Advance Programme
is now available -
see the programme page
How
to get to Barcelona and an hotel registration form are available -
see the venue
page
Registration to the conference
is now activated - You
may register on-line or download the blank form on the registration
page . Pay attention: advance registration is closed since Sept. 1st and online registration will be available only till Sept. 10th.
Special Attention to the Authors - Registration
deadline and submission of final papers is July
27th !
{
Important Dates}
Paper submissions
Special session & tutorial proposals
Notification of acceptance
Presenters registration
Final versions of accepted papers
Proposal for on-site meetings |
due April 30 May 11
due April 30
June 15
July 27
due July 27
September 03 |
{ What is FDL }
FDL is the European forum to exchange experiences and learn new
trends in the application of languages and their
associated design methods and tools for the design of electronic systems. The
Forum is organized around Thematic
Areas (TA) (described below) and includes working sessions, poster sessions,
embedded tutorials, panels and technical
discussions. Fringe meetings such as user group or standardization meetings are
also held in conjunction with the Forum.
{ The Thematic Areas}
PDV TA: Property-Driven Design, Verification & Debug
Chair: Dominique Borrione – TIMA Laboratory, France, Dominique.Borrione@imag.fr
The assertion of formal properties provides a uniform expression
of expected system behaviour, or constraints that are assumed
on the environment, for a variety of design tasks: verification
of functional correctness, generation of test stimuli, synthesis
of
observation monitors and on-line tests, model checking on the reachable
state space, direct synthesis from assertions, etc.
Standardized formalisms such as PSL and SystemVerilog, defined
with trace operational semantics, were initially intended for
synthesizable RTL; their application is now considered at transaction
levels and for mixed system designs. The PDV technical area
welcomes research contributions, tool demonstrations, reports on
standardization activities and effective applications in all aspects
of innovative property expression and processing, with an emphasis
on frontier design levels, verification, automatic synthesis and
mechanized debug aids.
CSD TA: C/C++-Based System Design
Chair: Frank Oppenheimer – OFFIS e.V., Germany, Frank.Oppenheimer@offis.de
The CSD TA addresses language-based modelling and design techniques
for simulation, debugging, transformation and analysis
of hardware/software embedded systems. C/C++ based design methodologies
are entering productive industrial design flows
especially after the IEEE standardization of SystemC. Hence, the
lion share of contributions use SystemC and its extensions to
illustrate the scientific approach. However, articles using languages
like UML, functional languages, System Verilog are very
welcome, especially if they address interoperability between modelling
languages and heterogeneous models of computations.
Topics of interest also include embedded software modelling techniques
and technology or domain specific approaches, e.g. for
signal processing applications or reconfigurable computing platforms.
New mechanisms for abstraction like transaction level
modelling (TLM) or SPIRIT and their implications on IP-based system
design or system synthesis are in the scope of this workshop
as well as innovativeindustrial case studies.
AMS TA: Analog, Mixed-Signal, and Heterogeneous System Design
Chair: Sorin A. Huss – Technische Universität Darmstadt,
Germany, huss@iss.tu-darmstadt.de
Modern information processing systems frequently combine analog,
RF, power electronic, or even non-electrical components with
complex digital hardware and an increasing share of software. The
combination and tight interaction of such components is a
challenge: Specification, modelling, simulation, (symbolic) analysis,
verification, design, (virtual) prototyping, or even synthesis
of
analog, mixed-signal, and heterogeneous systems are highly complex
issues. Furthermore, physical effects are of an increasing
impact and have to be considered even at system level. Languages,
models, representations, and tools such as VHDL-AMS, Verilog-
AMS, SystemC-AMS, Modelica, Matlab/Simulink, or Hybrid Automata
are emerging to support such issues starting from transistor
level up to system level. The AMS Thematic Area aims at presenting
latest research activities, design experiences, and
standardization issues related to these topics.
UML TA: UML-Based System Specification & Design
Chair: Pierre Boulet – LIFL, Lille, France, Pierre.Boulet@lifl.fr
Model driven methods, mostly based on the Unified Modelling Language,
increasingly support semi-formal methods for system level
design of complex embedded systems including highly programmable
platforms and heterogeneous Systems-on-Chip.
Current design methods do not close the gap from specification
to (automatic) synthesis yet. UML related research topics in this
field are Executable UML, model driven development (MDA, PIM, PSM),
model transformations, UML semantics, metamodels (e.g.,
for SystemC and other System Description Languages or HDLs), UML
profiles, formalization of UML towards domain specific
languages for simulation and synthesis. Other welcomed topics are
standardization work, Real-time UML, model driven techniques
for performance analysis, validation and verification, SDL, OCL,
XMI and practical design experiences with UML2. |