A SIG-VHDL event sponsored by ECSI,
co-sponsored by ENS Lyon and INSA Lyon,
and with no financial implication by
Accellera, ACM-SIGDA, Cadence, IEE, IFIP 10.5, ITG, GI, GMM, Mentor Graphics, VDE, SEE, VSIA

 

 

The Forum on Design Languages (FDL) is the European forum to exchange experiences and learn of new trends, in the application associated design methods and tools, to design electronic systems. By offering several co-located events, this multi-faceted forum gives an excellent opportunity to gain up-to-date knowledge across a wide field. FDL’01 is the fourth in this series after Lausanne, Lyon, Tübingen, ENS Lyon has been chosen again to host FDL’01.

The forum is organized around several interrelated workshops with working sessions and technical discussion.

The workshop on hardware description languages started on 1989 with VUFE. This year it addresses standardization efforts at different abstraction levels, analog and mixed signal as well as C/C++ based languages. Tuesday hosts Hardware Description Languages (HDL) sessions together with C/C++ based HW/SW Specification & Design (CCSD) sessions. On Wednesday, CCSD continues and Analog & Mixed Signal Specification (AMS) begins.

The Design Environments & Languages (DEL) workshop, on Tuesday, is dedicated to EDA distributed environments that mostly come with a combination of graphical and textual design languages.

System Specification & Design Languages (SSDL) started in 1996, as SLDL, to address the need of specifying embedded systems or systems-on-chip. In FDL’01, on Wednesday and Thursday, SSDL also includes Real Time Specification for Embedded Systems (RTSE) and Architecture Modeling and Reuse (AMR).

In addition, five half-day tutorials are provided on Monday to introduce the field. Interested participants select two tutorials.

During the forum, attendees are also able to freely follow hands-on-labs on Windows NT or Unix Solaris workstations.

FDL’01 is coordinated by INSA Lyon and the event is hosted by ENS Lyon located in the south of Lyon.