European Electronic Chips & Systems design Initiative

European Electronic
Chips & Systems
design Initiative

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System Verification Workshop - December 7, 2004 - Grenoble, France

Agenda (PDF format)

Presentation slides (PDF format)

The European Chip and Systems design Initiative (ECSI) is launching the preparation of the next ECSI Institute workshop, which will be devoted to System Verification.

The workshop addresses one of the hottest topics in system design methods, which is the rapidly increasing verification cost. Various verification techniques for system design will be discussed:

• Transaction Level Modelling and Verification Techniques
• SystemVerilog Verification Methodology Manual
• Assertion Based Verification
• IP Verification

These presentations will be preceeded by a system company point of view on verification methodology requirements and expected solutions in terms of a complete portfolio of complementary verification techniques.

Some presentations will be completed by demonstration sessions. Also the panel will be organised to enable exchange of minds between presenters and workshop participants.

Involved partners: ARM, Cadence, Mentor Graphics, STMicroelectronics, Synopsys

Workshop Description (PDF format)

Workshop Registration Form (PDF format)

Workshop Description (WORD format)

Workshop Registration Form (WORD format)

Previous Events: SDS, UML, ASDP, SysSynth

IP-SOC Conference (held in conjunction to this event)

Industry surveys show that for what is called "design", actually 70% of the effort go into verification, telling that "debugging takes twice as long as coding." With the increasing complexity of systems on chips (SoCs), verification problems will be even harder to tackle:

• Are current methods capable of coping with the increasing complexity?
• Systems on chip contain an increasing amount of software. There is a need for efficient HW/SW co-verification methods. Are they available or at least in the foreseeable horizon?
• Assertion-based design: is it a reasonable step forward or only a partial solution to a much bigger problem?
• We have seen the development of dedicated verification-oriented languages: PSL, e, OpenVera™, … - each of them is suitable for certain verification tasks. What needs to be done to consolidate these languages? Is SystemVerilog the answer? How to achieve successful standardization and industry adoption?
• There are several formal verification methods supported by commercial tools, for example, property checking. How can these static verification concepts be combined with traditional dynamic verification flows based on simulation/emulation to increase the level of confidence and verification productivity?
• There is a need for the specification of testbenches possibly at the system level and to use them throughout the entire design and implementation process. What are the obstacles to make it a reality for designers?
• There is much talk about measuring Verification progress and the value of coverage tools; What level of confidence in the quality of the verification process and the suitability of the testbenches can they offer?
• It is the assumption that the provision of verification solutions should focus on a complete as possible verification methodology and on standard languages, not on dedicated tools. How far are we from this objective? What is the current industrial status?
• Historically, vendor specific languages had a prominent role in the verification domain. What will be their role in the future?

The objective of the workshop is to show concrete proposals and solutions to solve some of the problems mentioned above. The presentations are supposed to be industry relevant. The presentations should be methodology oriented, rather than tool focused.

ECSI System Verification Workshop Agenda

Workshop Sessions

Session 1: “A User's Perspective: System Verification Requirements & SystemC-based Verification Methodology”
Abstract: This presentation will focus first on requirements for the system verification methods from the perspective of a verification methods user. Then the SystemC TLM methodology will be presented together with the associated verification tasks.
Presenter: Stephane Guenot/Alain Clouard, ST Microelectronics - Duration: 60 min

Session 2: “Assertion Based Verification IP: Methodology and Key Industry Drivers”
Abstract: There have been significant maturing of standards and tools directed at providing robust verification solutions. In parallel, there is a strong focus from EDA vendors to provide Assertion Based Verification IP. Now, designers and verification engineers are clear on the value but there is a variety of methodologies which are used in the industry. This presentation looks at first the standards, then the verification methodologies and then who is driving the need for IP. What is compelling value in ABV IP? How will the adoption grow in the next few years? How will it evolve verification methodology? There will be reference to solutions from Mentor Graphics in this area.
Presenter: Kanwel Thapar, Mentor Graphics Europe - Duration: 40min

Session 3: “Verification Interfaces & Components Library”
Abstract: The capacity, speed, and capability of so-called “conventional” verification techniques have not kept pace with the ever-growing scope and ever-shrinking time-to-market windows of the designs and systems being developed today. The best paths, or methods, are ones that emphasize efficient use of resources, fast turn-around within iterative processes, and getting predictable, reliable, correct results. With the infrastructure provided by the Verification Interfaces & Components (VIC) libraries, component developers can focus immediately on the intended function rather than figure out how to best leverage SystemC and the SCV library for their designs. Test writers benefit because the components would have a common user-interface.
Presenter: Jean-Yves Pateyron, Cadence - Duration: 40 min

Session 4: “Tutorial: SystemVerilog Verification Methodology Manual”
Abstract: The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language to include enhanced modeling and verification features. The integration of verification features creates a unified language that brings enhanced design and advanced verification technologies, including assertions, together to deliver increased designer productivity and more effective verification. This tutorial will provide an overview of the SystemVerilog Verification Methodology Manual (VMM), jointly developed by verification experts from Synopsys and ARM, and will show the benefits of unifying the advanced design and verification features of SystemVerilog, using assertions, object-oriented programming, random stimulus, constraint solving and functional coverage.
Presenter: Janick Bergeron, Synopsys/ARM - Duration: 120 min
Janick Bergeron is the author of the best-selling book "Writing testbenches: functional verification of HDL models" and the moderator of the Verification Guild. He is also a co-author of the upcoming "SystemVerilog Verification Methodology Manual".